1. Field
Example embodiments relate to a semiconductor device and methods of manufacturing the same. Other example embodiments relate to a capacitorless DRAM and methods of manufacturing the same.
2. Description of the Related Art
A memory cell of a conventional dynamic random access memory (DRAM) has a 1T/1C structure in which one transistor and one capacitor are included. Because the conventional DRAM includes a transistor and a capacitor, reducing the cell area of the conventional DRAM to a size of about 4F2 (F: feature size) or less may be difficult. In respect to reducing the size of DRAM devices, a DRAM that may store data using only the transistor without the capacitor, e.g., a capacitorless 1T DRAM, has been proposed. The capacitorless 1T DRAM may have an electrically floated channel body.
FIGS. 1A and 1B are cross-sectional views of a conventional capacitorless DRAM and a method of operating the conventional capacitorless DRAM. Referring to FIGS. 1A and 1B, a gate 110 may be formed on a silicon on insulator (SOI) substrate 100. The SOI substrate 100 may have a structure in which a first silicon layer 10, an oxide layer 20, and a second silicon layer 30 are sequentially stacked, and the gate 110 may have a structure in which a gate insulating layer 40 and a gate conductive layer 50 are sequentially stacked. A source 30a and a drain 30b may be formed in the second silicon layer 30 on either side of the gate 110. A floating channel body 30c, that is electrically separated from the first silicon layer 10, may be formed between the source 30a and the drain 30b. The floating channel body 30c may be a partially depleted region having a thickness of about 150 nm.
As illustrated in FIG. 1A, when voltages of 0.6V, 0V, and 2.3V are respectively applied to the gate conductive layer 50, the source 30a, and the drain 30b, electrons migrate from the source 30a to the drain 30b through the floating channel body 30c. In this process, electron-hole pairs are generated by electron impact in the floating channel body 30c. The holes may not leave the floating channel body 30c but accumulate in the floating channel body 30c. The holes may be called excess holes 5. A state when the excess holes 5 accumulate in the floating channel body 30c is a first state.
As illustrated in FIG. 1B, when voltages of 0.6V, 0V, and −2.3V are respectively applied to the gate conductive layer 50, the source 30a, and the drain 30b, a forward bias may be applied between the floating channel body 30c and the drain 30b. The excess holes 5 of FIG. 1A may be removed from the floating channel body 30c, and electrons 7 may accumulate in the floating channel body 30c. A state when the electrons 7 accumulate in the floating channel body 30c is a second state. Because the floating channel body 30c has different resistances in the first and second states, the first and second states may be used to represent different data states, e.g., ‘1’ and ‘0’.
However, in the conventional capacitorless DRAM, the floating channel body 30c may have undesirable data retention properties. In the conventional capacitorless DRAM, a relatively wide area of the floating channel body 30c may contact the source 30a and the drain 30b. Thus, a relatively large amount of charges may be lost at the corresponding junctions. Accordingly, data retention time in the floating channel body 30c may be reduced.